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| IP113M LF Preliminary Data Sheet Managed 10/100Base-TX / FX Media Converter Features A 10/100BASE-TX/ 100BASE-FX converter with a SMI port for management Built in a 10/100BASE-TX transceiver Built in a PHY for 100BASE-FX Built in a 2-port switch - Pass all packets without address and CRC check (optional) - Supports modified cut-through frame forwarding for low latency - Supports pure converter mode data forwarding for extreme low latency - Supports flow control for full and half duplex operation - Bandwidth control - Max packet length 1600 bytes - Optional forward fragments Built in 128Kb RAM for data buffer Supports 3.3v I/O tolerance SMI (MDC, MDIO) and MII registers for management - Configure local and remote IP113M LF through local SMI - Monitor local and remote IP113M LF through local SMI - Configure/ monitor TP port support (auto-negotiation or force 10M/100M, full/half) - Configure/ monitor flow control, bandwidth - Supports loop back test (In-band or out-band, auto or program) - The maintenance frame is compliant to TS-1000 standard (the Telecommunication Technology Committee, TTC) Supports Statistic Counters Supports auto MDI-MDIX function Supports link fault pass through function Supports far end fault function LED display for link/activity, full/half, 10/100 Built in a watchdog timer to monitor internal switch error Supports EEPROM Configuration 0.25u CMOS technology Single 2.5V power supply 48-pin LQFP package Support Lead Free package (Please refer to the Order Information) General Description IP113M LF can be a 10/100BASE-TX to 100BASE-FX converter with an SMI port for management. It consists of a 2-port switch controller, a fast Ethernet transceiver and a PHY for 100BASE-FX. The transceivers in IP113M LF are designed in DSP approach with advance 0.25um technology; this results in high noise immunity and robust performance. IP113M LF not only supports store and forward mode, it also supports modified cut through mode and pure converter mode for low latency data forwarding. IP113M LF can transmit packet(s) up to 1600 bytes to meet requirement of extra long packets. IP113M LF supports remote management function. IP113M LF supports remote access functions and it also supports remote monitor and loop back test function defined in TS-1000 spec (*). Local IP113M LF can access the MII registers of remote IP113M LF by programming local IP113M LF's MII registers via SMI connection. IP113M LF implements the management function using the maintenance frame defined in TS-1000 spec. IP113M LF supports IEEE802.3x, collision base backpressure, and various LED functions, etc. These functions can be configured to fit the different requirements by feeding operation parameters via EEPROM interface or pull up/down resistors on specified pins. * The Telecommunication Technology Committee owns the copyright of TS-1000. 1/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Contents Features....................................................................................................................................................... 1 General Description..................................................................................................................................... 1 Contents ...................................................................................................................................................... 2 Revision History........................................................................................................................................... 4 Block Diagram ............................................................................................................................................. 5 Application Diagram .................................................................................................................................... 5 Applications ................................................................................................................................................. 6 Managed converter (up to 31 pieces of IP113M LF in a chassis) ............................................................... 6 Un-managed converter................................................................................................................................ 6 PIN Diagram ................................................................................................................................................ 7 1. PIN Description ................................................................................................................................... 8 PIN Description (continued).............................................................................................................. 9 PIN Description (continued)............................................................................................................ 10 PIN Description (continued).............................................................................................................11 PIN Description (continued)............................................................................................................ 12 PIN Description (continued)............................................................................................................ 13 2. Functional Description ...................................................................................................................... 14 2.1 Data forwarding ................................................................................................................ 14 2.1.1 Modified cut-through mode................................................................................... 14 2.1.2 Pure converter mode ............................................................................................ 14 2.1.3 Fragment forwarding ............................................................................................ 14 2.2 TP port force mode ........................................................................................................... 15 2.3 Remote management ....................................................................................................... 16 2.3.1 Maintenance frame format at MII ......................................................................... 16 2.3.2 Bit definition of maintenance frame ...................................................................... 16 2.3.3 Bit definition of maintenance frame (continued)................................................... 17 2.3.4 Remote monitor .................................................................................................... 18 2.3.5 Remote control read ............................................................................................. 18 2.3.6 Remote control write............................................................................................. 18 2.4 Loop back test .................................................................................................................. 19 2.4.1 Out-band loop back test ....................................................................................... 19 2.4.2 In-band loop back test .......................................................................................... 21 2.4.3 Programming procedure for In-band loop back test............................................. 22 2.4.4 Auto in-band loop back test.................................................................................. 22 2.5 Remote monitor without SMI programming...................................................................... 23 2.5.1 Auto sends (Status change notice)....................................................................... 23 2.6 Link fault pass through ..................................................................................................... 24 2.6.1 Normal case ......................................................................................................... 24 2.6.2 Remote TP port disconnected .............................................................................. 24 2.6.3 FX port disconnected .............................................................................................. 25 2.6.4 LED diagnostic functions for fault indication ........................................................ 25 2.7 EEPROM - store the initial value ..................................................................................... 26 2.8 Auto MDI_MDIX................................................................................................................ 27 2.9 Serial management interface............................................................................................ 28 3. MII registers ...................................................................................................................................... 29 3.1 The basic MII registers ..................................................................................................... 30 The basic MII registers 0 ................................................................................................ 30 The basic MII registers 1 ................................................................................................ 32 The basic MII registers 1(continued).............................................................................. 33 The basic MII registers 2 , 3 ........................................................................................... 34 The basic MII registers 4 ................................................................................................ 35 The basic MII registers 5 ................................................................................................ 36 2/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet The basic MII registers 6 ................................................................................................ 37 3.2 Extended MII registers and EEPROM registers ............................................................... 38 Extended MII registers and EEPROM registers 16........................................................ 39 Extended MII registers and EEPROM registers 17........................................................ 40 Extended MII registers and EEPROM registers 17(continued)...................................... 41 Extended MII registers and EEPROM registers 18........................................................ 42 Extended MII registers and EEPROM registers 19........................................................ 43 Extended MII registers and EEPROM registers 20........................................................ 44 Extended MII registers and EEPROM registers 20(continued)...................................... 45 Extended MII registers and EEPROM registers 21........................................................ 46 Extended MII registers and EEPROM registers 22........................................................ 47 Extended MII registers and EEPROM registers 22(continued)...................................... 48 Extended MII registers and EEPROM registers 23........................................................ 49 Extended MII registers and EEPROM registers 23(continued)...................................... 50 Extended MII registers and EEPROM registers 24........................................................ 51 Extended MII registers and EEPROM registers 25........................................................ 52 Extended MII registers and EEPROM registers 26........................................................ 53 Extended MII registers and EEPROM registers 27,28,29,30......................................... 54 Extended MII registers and EEPROM registers 31........................................................ 55 Electrical Characteristics .................................................................................................................. 57 4.1 Absolute Maximum Rating................................................................................................ 57 4.2. DC Characteristic ............................................................................................................ 57 Order Information.............................................................................................................................. 57 Package Detail.................................................................................................................................. 58 4. 5. 6. 3/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Revision History Revision # Change Description IP113M LF-DS-R01 Initial release. IP113M LF-DS-R02 IP113M LF-DS-R03 IP113M LF-DS-R04 Remove Operation Junction Temperature. IP113M LF-DS-R05 TP port should be linked at 100M full duplex when working at this mode. IP113M LF-DS-R06 Update page 42,1 IP113M LF-DS-R07 Add the order information for lead free package. Update page 50 (Item:31.2 & 31.3) IP113M LF-DS-R08 Update page 27 Update the default value of following resisters MII reg3.[5:4], reg4.10, reg6.2, reg16.6, reg18.3, reg18.13, reg22.4, reg22.6, reg23.13 and Description of reg26.0 Add explanation to MII reg31.[5:4], reg31.3, reg31.2 IP113M LF-DS-R09 Revise the diagram. IP113M LF-DS-R10 Modify the IPL : pull-low and IPH : pull-high on page 8. IP113M LF-DS-R11 Add Power Pin description on Page13 4/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Block Diagram MDC MDIO MII registers SSRAM PLL/ Clock Generator RXIP RXIM TXOP TXOM 10/100M TX PHY MII Two port switch MII 100M FX FXSD FXRDP FXRDM FXTDP FXTDM SCL SDA EEPROM I/F Forward Mode Control LED I/F LED Remote Control Application Diagram FX Fiber Module IP113M LF TX 5/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Applications Managed converter (up to 31 pieces of IP113M LF in a chassis) VCC FAST_FWD MDC, MDIO IP113M LF uC (for management) X1 X 31 Un-managed converter 10BASE_T/1 00BASE-TX PHY1 SWITCH 100BASE-FX PHY2 RAM IP113M LF 6/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet PIN Diagram LED_FX_SD/ SPEED_MODE 38 SCL / ADDR0 MDIO OSCI MDC GND GND VCC 48 47 46 44 43 42 41 40 39 VCC SDA X2 37 36 35 34 33 32 45 LED_FX_FDX/ ADDR2 AVCC BGRES AUTO_TEST GND RXIP RXIM AVCC TXOP TXOM GND AVCC ADDR1 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 12 LED_FX_LINK/ FX_FULL GND_IO VCC_IO LED_TP_SPD LED_TP_FDX/ ADDR3 LED_TP_LINK/ ADDR4 LED_FX_FEF_DET/ DUPLEX_MODE LED_RMT_TP_LINK/ X_EN RESETB TSE TSM LED_RMT_TP_SPD/ AUTO_SEND IP113M LF 31 30 29 28 27 26 25 INTB 7/58 Copyright (c) 2004, IC Plus Corp. LED_RMT_TP_FDX/ TP_FORCE DIRECT_WIRE FXRDP FXRDM FAST_FWD FXTDP FXTDM FXSD VCC GND LFP April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 1. PIN Description Type I O IPH IPL Description Input pin Output pin Input pin with internal pull-high resistor Input pin with internal pull-low resistor Pin no. Label Type I O O TP receive TP transmit Description Transceiver 5, 6 RXIP, RXIM 8, 9 2 TXOP, TXOM BGRES Band gap resistor It is connected to GND through a 6.19k (1%) resistor in application circuit. 100Base-FX signal detect Fiber signal detect. It is an input signal from fiber MAU. Fiber signal detect is active if the voltage on FXSD is higher than the threshold voltage, which is 1.35v 5% when VCC is equal to 2.5v. Fiber receiver data pair Common-mode voltage of FXRDP and FXRDM are suggested to near 0.5x AVCC. When voltage peak-to-peak>0.1V,FXRX could be workable. Fiber transmitter data pair FXTX with the external 100 resistor. Common-mode voltage of FXTDP and FXTDM are suggested to near 0.5x AVCC. Swing of Voltage 0.8V. 18 FXSD I 13, 14 FXRDP, FXRDM I 16, 17 FXTDP, FXTDM O 8/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet PIN Description (continued) Pin no. LED pins 31 Label LED_TP_LINK Type O Description TP port link LED On: link ok, Off: link fail, Flash: link ok & activity (Flash: on for 20ms and off for 80ms) TP port speed LED On: 100M, Off: 10M TP port full duplex LED On: full, Off: half, Flash: half & collision happens (Flash: on for 20ms and off for 80ms) Fiber port link LED On: link ok, Off: link fail, Flash: link ok & activity (Flash: on for 20ms and off for 80ms) Fiber port full duplex LED On: full, Off: half, Flash: half & collision happens (Flash: on for 20ms and off for 80ms) Fiber port signal detect On: FXSD is active, Off: FXSD is inactive Far end fault pattern received Far End Fault Pattern received: LED On: 80ms, LED Off: 20ms Far End Fault Pattern not Receive: LED is always off 29 LED_RMT_TP_LINK O LED for link status of TP port of remote IP113M LF Pin 3 AUTO_TEST = 0 Pin 3 AUTO_TEST = 1 On: link ok, Flash Off: link fail (On: 80ms, Off: 20ms) LED for speed of TP port of remote IP113M LF Pin 3 AUTO_TEST = 0 Pin 3 AUTO_TEST = 1 On: 100M, On: loop back test complete, Off: 10M Off: under loop back test LED for full duplex of TP port of remote IP113M LF Pin 3 AUTO_TEST = 0 On: full duplex, Off: half duplex Note: The output of LED pin is logic low when the LED is on. Pin 3 AUTO_TEST = 1 On: loop back test result is ok, Off: loop back test result fails 33 32 LED_TP_SPD LED_TP_FDX O O 36 LED_FX_LINK O 37 LED_FX_FDX O 38 30 LED_FX_SD LED_FX_FEF_DET O O 25 LED_RMP_TP_SPD O 24 LED_RMT_TP_FDX O 9/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet PIN Description (continued) Pin no. Label Type Description LED pins used as initial setting mode during reset 29 X_EN IPH Flow control enable on TP port and fiber port 1: enable (default), 0: disable 24 TP_FORCE IPL Local TP port auto negotiation enable 1: TP port supports auto-negotiation with limited capability defined by pin 38 SPEED_MODE and pin 30 DUPLEX_MODE. 0: TP port supports auto-negotiation with 10M/100M, full/ half capability (default) The setting may be updated by programming EEPROM register 3.5 or MII register 20.13. 38 SPEED_MODE IPH Local TP port speed selection 1: TP port has the 100Mb speed ability 0: TP port has the 10Mb speed ability only It is valid only if pin 24 TP_FORCE is enabled. 30 DUPLEX_MODE IPH Local TP port duplex selection 1: TP port has the full duplex ability 0: TP port has the half duplex ability only It is valid only if pin 24 TP_FORCE is enabled. 25 AUTO_SEND IPL Auto send the status to the remote IP113M LF 1: enable 0: disable (default) Set the duplex of fiber port 1: full duplex (default) 0: half duplex Auto loop back test 1: enable When IP113M LF detects a low-to-high transition on this pin, it will perform loop back test for once. It supports an easy way to instruct IP113M LF performing fiber loop back test without programming MII registers. 0: disable (default) 36 FX_FULL IPH 3 AUTO_TEST IPL 10/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet PIN Description (continued) Pin no. Label Type Description LED pins used as initial setting mode during reset 11/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet PIN Description (continued) Pin no. Label Type IPL Description Link fault pass through (LFP) 1: enable Link status of one port is forwarded to the other port. 0: disable (default) DIRECT_ FAST_F Function WIRE WD 0 0 Store and forward switch mode (default) 0 1 1 1 0 1 Modified cut-through switch mode Converter mode Converter mode with auto-change-forward function MC operation mode 21 LFP 22 23 DIRECT_WIRE FAST_FWD IPL Store and forward switch mode: IP113M LF begins to forward a frame at the end of receiving a frame completely. Modified cut-through switch mode: IP113M LF begins to forward a frame after the first 64 bytes data received. TP port should be forced at 100M at this mode. Converter mode: Incoming frames are not buffered in IP113M LF to achieve the min latency. Both TP port and fiber port of IP113M LF should work at 100M full duplex in this mode. If TP port is linked at half duplex, the total length of UTP cable and fiber should be less than 60 meters to meet the requirement of CSMACD in IEEE802.3. Converter mode with auto-change-forward function: IP113M LF will change forward mode itself if it detects the speed is different in TP port and FX port. In converter mode, IP113M LF forwards IEEE802.3x pause frame directly. In the other modes, IP113M LF doesn't forward IEEE802.3x pause frame directly, it sends out pause frame when its internal buffer is full. 12/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet PIN Description (continued) Pin no. Label Type I, IO Description SMI interface The external MAC device uses the interface to program IP113M LF. MDIO is an open drain. PHY address The external MAC device uses the address to identify each IP113M LF in a chassis. IP113M LF also uses ADDR[2:0] as EEPROM address A[2:0] to read EEPROM. SMI interface 47, 48 MDC, MDIO 31, 32, 37, 12, 46 ADDR[4:0] IPL Pin no. 45, 46 Label SDA, SCL Type IPH, O EEPROM interface Description EEPROM interface Pin no. Misc. 28 41, 40 Label RESETB OSCI, X2 Type I I, O Reset It is low active. Crystal pins Description OSCI and X2 are connected to a 25Mhz crystal. If a 25MHz oscillator is used, OSCI is connected to the oscillator's output and X2 should be left open. 26, 27 TSM, TSE IPL Scan pins These two pins should be left open or connected to ground for normal operation. Interrupt 0: an interrupt happens. Its output is low. 1: no interrupt. Its output is high impedance and it needs an external pull up resistor. 15 INTB O Pin no. Power 1,7,11 19,39,44 34 35 4,10,20, 42,43 AVCC Label Type 2.5V Analog Power Description VCC VCC_IO GND_IO GND 2.5V Digital Power 3.3V or 2.5V Digital Power I/O Ground Ground 13/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 2. Functional Description 2.1 Data forwarding IP113M LF supports three types of data forwarding mode, store & forward mode, modified cut-through mode and pure converter mode. It can forward a frame despite of its address and CRC error. IP113M LF begins to forward the received data when it receives the frame completely. The latency depends on the packet length. 2.1.1 Modified cut-through mode IP113M LF begins to forward the received data when it receives the first 64 bytes of the frame. The latency is about 512 bits time width. The maximum packet length is up to1600 bytes in this mode. Please refer to pin description of FAST_FWD for configuration information. 2.1.2 Pure converter mode IP113M LF operates with the minimum latency in this mode. The transmission flow does not wait until entire frame is ready, but instead it forwards the received data immediately after the data being received. Both transceivers are interconnected via internal MIIs and the internal switch engine and data buffer are not used. Both TP port and fiber port of IP113M LF should work at 100M full duplex in this mode. If TP port is linked at half duplex, the total length of UTP cable and fiber should be less than 60 meters to meet the requirement of CSMACD in IEEE802.3. The packet length is not limited at this mode. Please refer to pin description of DIRECT_WIRE for configuration information. In converter mode, it is strongly recommended that both TP port and fiber port of IP113M LF should work at 100M full duplex. If TP port is linked at half duplex, the UTP cable length should be less than 30 meters to meet the requirement of CSMACD in IEEE802.3. 2.1.3 Fragment forwarding IP113M LF forwards CRC error packets but it will filter fragments when it works in modified cut-through mode. IP113M LF forwards fragments if user turns on bit 3 of MII register 20. 14/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 2.2 TP port force mode The TP port of IP113M LF can work at auto mode or force mode. The following table shows all of the combination of its TP port. Link partner's capability AN on {TP_FORCE, SPEED_MODE, DUPLEX_MODE} 011 010 001 000 111 110 101 100 IP113M LF's link result IP113M LF's capability 100/10M, Full/Half, AN on 100/10M, Half, AN on 10M, Full/Half, AN on 10M, Half, AN on 100M, Full, AN on 100M, Half, AN on 10M, Full, AN on 10M, Half, AN on 100F 100H X X X 100F X X X 100H X X X 100H X X 10F X 10F X X X 10F X 10H 100H 100H 10H 10H 100H 100H 10H 10H 100H 100H 10H 10H 100H 100H 10H X X X 10H 100F 100F 100H 100H X X X X X X 10F 10H 10H 10H 10H 10H X X 10F 10H 100F 100H 10F 10H AN off 100F 100H 10F 10H Note: AN on: with auto-negotiation capability AN off: without auto-negotiation capability 100F: 100M full duplex 100H: 100M half duplex 10F: 10M full duplex 10H: 10M half duplex 15/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 2.3 Remote management IP113M LF supports remote monitor and configuration function. IP113M LF implement the function by exchanging maintenance frames on fiber ports between two IP113M LF's. The maintenance frames are not forwarded to TP ports. The frame format follows the TS-1000 standard. 2.3.1 Maintenance frame format at MII TXD0 F0 F4 C0 C4 C8 C12 S0 S4 S8 S12 M0 M4 M8 M12 M16 M20 M24 M28 M32 M36 M40 M44 E0 E4 TXD1 F1 F5 C1 C5 C9 C13 S1 S5 S9 S13 M1 M5 M9 M13 M17 M21 M25 M29 M33 M37 M41 M45 E1 E5 TXD2 F2 F6 C2 C6 C10 C14 S2 S6 S10 S14 M2 M6 M10 M14 M18 M22 M26 M30 M34 M38 M42 M46 E2 E6 TXD3 F3 F7 C3 C7 C11 C15 S3 S7 S11 S15 M3 M7 M11 M15 M19 M23 M27 M31 M35 M39 M43 M47 E3 E7 TXEN 2.3.2 Bit definition of maintenance frame Bit Item F7 - F0 C0 C1 Preamble Discriminator for the maintenance signal Direction 01010101 0 Description Note Fixed Fixed 0: terminal MC central MC 1: central MC terminal MC (MC: media converter) 00: Reserved 10: Indication 01: Request 11: Acknowledge 0000 C15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C8 01 00 C3 - C2 Command C7 - C4 C15 - C8 Version Control signal Fixed Function Loop test start Loop test finished Status indication R/W link partner's registers 0 R/W 10 11 Address [4:0] S0 S1 S2 S3 S4 S5 Condition of power Situation of receiving optical power Terminal/ network side link MC (media converter) fails 0: normal, 1: power off 0: normal, 1: abnormal 0: link up, 1: link down If S11="1", S2="X" 0: normal, 1: abnormal Informing way for optical 0: maintenance frame receiving power off 1: Far end fault indication Status indication for loop test 0: normal mode, 1: under loop test 16/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 2.3.3 Bit definition of maintenance frame (continued) Bit Item S6 Information for notice of terminal link status (Available for option B or not) Description Note 0: terminal IP113M LF does not support option B. 1: terminal IP113M LF supports option B, which can inform speed, duplex, and auto-negotiation in terminal IP113M LF. If S11 = "1", S6="X' 00: 10 Mbps 01: 100 Mbps 10: 1000 Mbps 11: others It is valid, if S6 = "1". If S2 or S11 = "1", S7, S8 = {X, X} 1: full duplex, 0: half duplex It is valid, if S6 = "1". If S6 ="0", S9="0". If {S7, S8} = {1,1}, S9="X" If S2 or S11 = "1", S9="X" 1: available, 0: un-available It is valid, if S6 = "1". If S6 ="0", S10="0". If {S7, S8} = {1,1}, S10="X" If S11 = "1", S10="X" 0: one UTP 1: more than one UTP Vender code for TTC standard It is C30900h. Specified by vender It is 000000h. CRC - 8 FCS calculation area: C0 - M47 S8 - S7 Terminal link speed S9 Duplex for the terminal side S10 Auto-negotiation capability for the terminal side S11 S15 - S12 M23 - M0 M47 - M24 E7 - E0 Number of interface in Terminal/ network side Reserved Vender code Model number FCS 17/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 2.3.4 Remote monitor Refer to the diagram below, users can instruct central IP113M LF, on the right, to issue a status request frame to get status defined in TS-1000 by programming MII register 24. The terminal IP113M LF, on the left, receives the status request frame and sends out its current status as a response frame onto the fiber port when it is available. The central IP113M LF receives the status frame and stores the status of terminal IP113M LF to its MII register 23. An acknowledge maintenance frame is store to MII register 26~30. The status of terminal IP113M LF is shown on the LEDs of central IP113M LF. (1) TP IP113M LF (terminal) Maintenance frame (C1=1, C2-3=10, C8-15=01000000) FX Maintenance frame (C1=0, C2-3=11, C8-15=01000000) (2) IP113M LF (central) (MII reg 24, 23) TP MDC, MDIO 2.3.5 Remote control read Users can instruct central IP113M LF to issue a remote control read frame to read the MII register of terminal IP113M LF by programming MII register 24. The bits [11:7] of the register 24 are filled with the address of register and bits [6:4] of the register 24 are filled with "011". The terminal IP113M LF receives the frame and sends out the content of the MII register to central IP113M LF when it is available. The central IP113M LF receives the frame and stores the data to MII register 27. An acknowledge maintenance frame is stored to MII register 26~30. The status of terminal IP113M LF is shown on LED of central IP113M LF. TP IP113M LF (terminal) Maintenance frame (C1=1, C2-3=10, C8-15=110xxxxx) FX IP113M LF (central) (MII reg 24,27) TP Maintenance frame (C1=0, C2-3=11, C8-15=01000000) MDC, MDIO 2.3.6 Remote control write Users can instruct central IP113M LF to issue a configure frame to write the MII register of terminal IP113M LF by programming MII register 24 and 25. The bits [11:7] of the register 24 are filled with the address of register and bits [6:4] of the register 24 are filled with "111". MII register 25 defines the data. The terminal IP113M LF receives the configure frame, configures itself according to the content of the frame and sends out its current status as a response frame onto the fiber port when it is available. The status of terminal IP113M LF is shown on LED of central IP113M LF. TP IP113M LF (terminal) Maintenance frame (C1=1, C2-3=10, C8-15=111xxxxx) FX IP113M LF (central) (MII reg 24,25) TP Maintenance frame (C1=0, C2-3=11, C8-15=01000000) MDC, MDIO 18/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 2.4 Loop back test IP113M LF supports two kind of loop back test function, in-band loop back test and out-band loop back test. 2.4.1 Out-band loop back test Users can instruct central IP113M LF to issue a maintenance frame onto the fiber port by programming MII register 24 to request a loop back test. Central IP113M LF does not generate test frames and users need an external packet source from PC. 1. Disconnect switch port and instruct the terminal IP113M LF to perform loop back and disable terminal T2 timer by programming central IP113M LF through SMI (1) Maintenance frame (C1=1, C2-3=10, C8-15=10000000) IP113M LF (terminal) TP FX (2) IP113M LF (central) (MII reg 24) TP Switch Maintenance frame (C1=0, C2-3=11, C8-15=10000000) MDC, MDIO 2 . T e r m in a l IP 1 1 3 M L F r u n s a t lo o p b a c k m o d e TP S w itc h IP 1 1 3 M L F ( te r m in a l) TP ( M II r e g 0 .1 4 = 1 ) FX IP 1 1 3 M L F ( c e n tr a l) 3. PC forces test frames to central IP113M LF and terminal IP113M LF loops back the frames. test frame FX test frame IP113M LF (terminal) TP (MII reg 0.14=1) IP113M LF (central) TP PC 4. PC reports the loop back test result after sending all test frames . IP113M LF (terminal) TP (MII reg 0.14=1) FX IP113M LF (central) TP PC 19/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 5. Reconnect switch and instruct the central IP113M LF to end loop back test and enable T2 timer. (1) IP113M LF (terminal) TP Maintenance frame (C1=1, C2-3=10, C8-15=00000000) FX (2) IP113M LF (central) (MII reg 24) TP Switch Maintenance frame (C1=0, C2-3=11, C8-15=00000000) MDC, MDIO 20/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Loop back test (continued) 2.4.2 In-band loop back test Besides performing the loop back test with an external packet source, IP113M LF supports an easy alternative. IP113M LF sends out private maintenance frame to do loop back test. All users have to do is to program MII registers through SMI. 1. Disabe receive function of central TP port and instruct the terminal IP113M LF to perform loop back and disable T2 timer by programming central IP113M LF through SMI IP113M LF (terminal) TP Maintenance frame (C1=1, C2-3=10, C8-15=10000000) FX IP113M LF (central) (MII reg 24) TP Switch MDC, MDIO 2. Terminal IP113M LF runs at loop back mode and acknowledges with maintenance frame IP113M LF (terminal) TP (MII reg 0.14=1) Maintenance frame (C1=0, C2-3=11, C8-15=10000000) FX IP113M LF (central) TP Switch 3. Central IP113M LF forces test frames to terminal IP113M LF and terminal IP113M LF loops back the test frames. Central IP113M LF checks the received test frame. IP113M LF (terminal) TP (MII reg 0.14=1) test frame FX test frame IP113M LF (central) (MII reg 24,25) TP Switch MDC, MDIO 4. Central IP113M LF ends loop back test enables receive function of TP port and enable LP T 2 timer (1) IP113M LF (terminal) TP Maintenance frame (C1=1, C2-3=10, C8-15=00000000) FX (2) IP113M LF (central) (MII reg 24) TP Switch Maintenance frame (C1=0, C2-3=11, C8-15=00000000) MDC, MDIO 21/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Loop back test (continued) 2.4.3 Programming procedure for In-band loop back test Step Description C1 C3~C2 1 Set local IP113M LF TP receive disabled C15~C8 Note Set Reg. 20.14 off 2a 2 3 4 5 6 Set remote T2 timer disabled by maintenance frame Set remote IP113M LF to be loop back mode enabled by maintenance frame Remote IP113M LF sends back loop back acknowledge Send loop back test maintenance frame Remote IP113M LF send back acknowledge Local IP113M LF stores the loop back maintenance to Reg. 26~30 and checks CRC bit is in Reg. 26.12 Repeat step 4~6 continuously Set remote IP113M LF to be loop back mode disable by maintenance frame Remote IP113M LF sends back loop back acknowledge Set local IP113M LF TP receive enable 1 1 -1 -- 01 01 -01 -- 11 11 11 11 00 00 00 01 -11 01 10 11 --- Reg24 and Reg 25 TS-1000: loop back set -Reg24 and Reg 25 -- 7 8 9 10 -1 -01 -00 00 00 00 -TC-1000: loop back end -Set Reg. 20.14 on 2.4.4 Auto in-band loop back test Step Description 1 Set pin AUTO_TEST to "1" (The following step is executed automatically by IP113M LF) 1.1 1.2 1.3 1.4 1.5 2 3 Central IP113M LF sends loop back start request to remote IP113M LF and goes to CST2 state. Remote IP113M LF sends loop back start acknowledge to Central IP113M LF and enters loop back test mode. Central IP113M LF goes to CST1 state and begins sending 15 frames in 64 bytes. Remote IP113M LF loops back the received frames at the TP port's PMD sub-layer. Central IP113M LF checks the loop back frames and reports the result. The LED pin LED_RMT_TP_LINK is Flash (on 80ms / off 20ms) during the auto loop back test period (AUTO_TEST is "1"). The LED pin LED_RMT_TP_SPD indicates the loop back test complete (on) (when AUTO_TEST is "1"). The LED pin LED_RMT_TP_FDX indicates the loop back test ok (on) (when AUTO_TEST is "1") If another auto loop back test is needed, set AUTO_TEST to "0" and then "1". That is, AUTO_TEST is triggered whenever there is a low-to-high transition on this pin. 4 22/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 2.5 Remote monitor without SMI programming 2.5.1 Auto sends (Status change notice) IP113M LF sends out status frame without receiving status request frame if pin AUTO_SEND is pulled high. It sends out the first status frame onto the fiber port when the link status of fiber port has established. It sends out status frames when the status on TP port has changed. IP113M LF supports two types of frame. For a TS-1000 maintenance frame, C[9:8] is 2'b10 and S[15:0] is defined as that in TS-1000 standard. For an ICplus maintenance frame, C[9:8] is 2'b11 and S[15:0] is the content of MII register 22. It carries ICplus private defined information. User can select the frame type by programming MII register 20.10. Central IP113M LF uses the mechanism to get the status of the remote IP113M LF even if there is no SMI programming. Option A Central IP113M LF sends indication frames to terminal IP113M LF if its status is changed. IP113M LF (terminal) TP Maintenance frame (C1=1, C2-3=01, C8-9= 01) IP113M LF (central) TP status changed !! FX Option B Terminal IP113M LF sends indication frames to central IP113M LF if its status is changed. IP113M LF (terminal) TP status changed !! Maintenance frame (C1=0, C2-3=01, C8-9= 01) IP113M LF (central) TP FX CRC polynomial for maintenance frame: X8 + X2 + X + 1 data in CRC + data X0 X1 X2 X3 X4 X5 X6 X7 CRC calculation 23/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 2.6 Link fault pass through When link fault pass through function is enabled, link status on TX port will inform the FX port of the same device and vice versa. From the link fault pass through procedure illustrates in the figure below, if link fail happens on IP113M LF's TX port (1), the local FX port sends non-idle pattern to notice the remote FX port (2). The remote FX port then forces its TX port to link failed after receiving the non-idle pattern (4). In other words, this mechanism will alert the link fault status of local TX port to the remote converter's TX port, and the link status of the remote TX port will become off. Link status LED will also be off for both IP113M LF and its link partner. (3) fiber port gets remote link fault information remote IP113M LF (5) remote TP link is off (1) TP port link failed local IP113M LF Switch1 or NIC 1 UTP Fiber UTP Switch2 or NIC 2 link off (2) fiber port sends non-idle pattern (4) TP link fail The procedure of link fault pass through 2.6.1 Normal case remote Switch1 LED SW1 UTP IP113M LF Fiber IP113M LF UTP local Switch2 LED SW2 LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 Link LED on SW1 LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 Link LED on SW2 ON ON ON ON ON ON 2.6.2 Remote TP port disconnected remote Switch1 LED SW1 UTP disconnected IP113M LF Fiber IP113M LF UTP LED SW2 local Switch2 LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 Link LED on SW1 LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 Link LED on SW2 Off Off Off Off Off Off 24/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 2.6.3 FX port disconnected remote Switch1 LED SW1 UTP IP113M Fiber IP113M UTP local Switch2 LED SW2 LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 Link LED on SW1 LED_TP_LINK1 LED_FX_LINK1 LED_FX_LINK2 LED_TP_LINK2 Link LED on SW2 Off Off Off Off Off Off 2.6.4 LED diagnostic functions for fault indication LED_TP_LINK LED_FX_LINK LED_FX_SD LED_FX_FEF_DET Status Link ok Link ok & activity Remote TP link off Fiber RX off, Fiber TX/ RX off Fiber TX off On Flash Off Off Off On Flash Off Off Off On On On Off On Off Off Off Off Flash Note Flash: flash, period 100 ms Link fault pass through is enabled. 25/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 2.7 EEPROM - store the initial value IP113M LF supports two ways to load initial value of MII registers. The procedure is illustrated as below. 1. IP113M LF reads the default setting of MII register from pins IP113M LF pins 2. IP113M LF updates the default setting of MII by reading EEPROM. If there exists an EEPROM. EEPROM IP113M LF 3. After reading EEPROM, IP113M LF is virtually isolated from the EEPROM. Micro-controller can program both MII register and EEPROM. EEPROM uC IP113M LF SCL, SDA MDC, MDIO 4. IP113M LF reloads the content of EEPROM to recover the value in MII registers programmed by Micro-controller after power on reset. EEPROM IP113M LF 26/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 2.8 Auto MDI_MDIX IP113M LF supports auto MDI-MDIX. It is always enabled. The following is its application circuit for auto MDI-MDIX. RXIP RXIM RD + RD AVCC TXOP TXOM TD + TD AVCC IP113M LF 50 50 IP113M LF CT 50 50 CT MDI-MDIX 0.1u transformer 0.1u MDI-MDIX transformer GND GND IP113M LF's application circuit (auto MDI-MDIX on) 27/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 2.9 Serial management interface User can access IP113M LF's MII registers through serial management interface MDC and MDIO. A specific pattern on MDIO is used to access a MII register. Its format is shown in the following table. When the SMI is idle, MDIO is in high impedance. To initialize the MDIO interface, the management entity sends a sequence of 32 contiguous "1" and "start" on MDIO. Syatem diagram 113M LF MDC MDIO 113M LF MDC MDIO 113M LF MDC MDIO management entity Frame format Read Operation Write Operation MDC z z MDIO 1..1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 op A A A A A R R R R R TA b b b idle start code 4321043210 111 write PHY address = Reg address = 543 01h 00h 1 b 1 2 0 b 1 1 0 1 1 0 0 0 0 0 0 0 0 1..1 b b b b b b b b b b b idle 19876543210 0 Register data MDC MDIO z z z 1..1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 Z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1..1 idle start op code read A A A A A R R R R R TA b b b b b b b b b b b b b b b b 4321043210 1111119876543210 PHY address = Reg address = 543210 Register data 01h 00h idle 28/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 3. MII registers Address 0 Register Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Control Register Status Register PHY identifier Register 1 PHY identifier Register 2 AN Advertisement Register AN Link Partner Base Page Ability Register AN Expansion Register (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Special Control Register Interrupt Register Extended Status Register Statistic Counter Register Switch Configuration Register 1 Switch Configuration Register 2 Local Switch Extended Register Link Partner Switch Extended Status Register Remote Control Transmit Register 1 Remote Control Transmit Register 2 Remote Control Receive Register 1 Remote Control Receive Register 2 Remote Control Receive Register 3 Remote Control Receive Register 4 Remote Control Receive Register 5 Switch Configuration Register 3 Control NWAY NWAY NWAY NWAY NWAY NWAY NWAY NWAY NWAY NWAY SWITCH SWITCH SWITCH SWITCH SWITCH RMC RMC RMC RMC RMC RMC RMC SWITCH 29/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 3.1 The basic MII registers Description Read/Write Self-Clearing Read Only The default value is "1" and it depends on the setting of its corresponding pin. Type RC LL LH Pin(0) Description Read and Clear Latching Low Latching High The default value is "0" and it depends on the setting of its corresponding pin. Type R/W SC RO Pin(1) The basic MII registers 0 MII NAME R/W DESCRIPTION DEFAULT MII control register (address 00h) 0.15 Reset R/W SC 0.14 Loop back R/W 0.13 Speed Selection RW 0.12 Auto-Negotiation Enable RW 0.11 0.10 Reserved Isolate R/W R/W 1 = PHY reset 0 = normal operation This bit is self-clearing, IP113M LF will return a value of 1 before reset process is completed, and will not accept any write transaction of MII Management within reset process. Make any change to Auto-Negotiation or speed mode will cause IP113M LF reset again. 1 = Loop back mode 0 = normal operation When this bit is set, IP113M LF will be isolated from the network media, and the assertion of TXEN at the MII will not transmit data on the network. All MII transmit data path will return to MII receive data path in response to the assertion of TXEN. MII COL signal will remain de-asserted at all times, unless bit 0.7 (Collision Test) is set. Use has to wait about 100ms for loop back path ready. 1 = 100Mbps 0 = 10Mbps It is valid only if bit 0.12 is set to be 0. 1 = Auto-Negotiation Enable 0 = Auto-Negotiation Disable MII register 16.11 auto-MDI/MDIX should be disabled if auto-negotiation is disabled. This bit should be "0" for normal operation. 1 = electrically isolate PHY from MII 0 = normal operation When this bit is setting to 1, IP113M LF will be isolated from MII, and not respond to the TXD[3:0] and TXEN and keep CRS, RXDV and RXD[3:0] in high impedance, but will respond to management transactions. 0 0 Pin(1) 1 0 0 30/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet MII NAME R/W DESCRIPTION DEFAULT MII control register (address 00h) 0.9 Restart AutoRW Negotiation 0.8 Duplex mode R/W 0.7 Collision test enable R/W 0[6:0] Reserved R/W 1 = re-starting Auto-Negotiation 0 = Auto-Negotiation re-start complete Setting this bit to logic high will cause IP113M LF to restart an Auto-Negotiation cycle, but depend on the value of bit 0.12 (Auto-Negotiation Enable). If bit 0.12 is cleared then this bit has no effect, and change to Read Only. When an Auto-Negotiation cycle is being processed, write 0 into this bit has no effect. This bit is self-clearing after Auto-Negotiation process is completed. 1 = full duplex 0 = half duplex It is valid only if bit 0.12 is set to be 0. 1 = enable the collision test 0 = disable the collision test If setting this bit to logic 1, when MII TXEN signal is asserted, IP113M LF will assert the MII COL signal within 512BT (Bit Time, depend on 10Mbps or 100Mbps). When MII TXEN is de-asserted, then TP110 will assert MII COL signal within 4BT. Clearing this bit to logic 0 for normal operation Write as 0, ignore on read 0 Pin(1) 0 - 31/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet The basic MII registers 1 MII NAME R/W DESCRIPTION DEFAULT MII status register (address 01h) 1.15 100Base-T4 RO capable 1.14 100Base-X full duplex Capable RO 1.13 100Base-X half duplex Capable RO 1.12 10Base-T full duplex Capable RO 1.11 10Base-T half duplex Capable RO 1[10:7] 1.6 1.5 Reserved MF preamble Suppression Auto-Negotiation Complete RO RO RO 1 = 100Base-T4 capable 0 = not 100Base-T4 capable IP113M LF does not support 100Base-T4. This bit is fixed to be 0. 1 = 100Base-X full duplex capable 0 = not 100Base-X full duplex capable The default of this bit will change depend on the external setting of IP113M LF. If external pin setting without 100Base-X full duplex support, then this bit will change default to logic 0. 1 = 100Base-X half duplex capable 0 = not 100Base-X half duplex capable The default of this bit will change depend on the external setting of IP113M LF. If external pin setting without 100Base-X half duplex support, then this bit will change default to logic 0 1 = 10Base-T full duplex capable 0 = not 10Base-T full duplex capable The default of this bit will change depend on the external setting of IP113M LF. If external pin setting without 100Base-T full duplex support, then this bit will change default to logic 0 1 = 10Base-T half duplex capable 0 = not 10Base-T half duplex capable The default of this bit will change depend on the external setting of IP113M LF. If external pin setting without 100Base-X full duplex support, then this bit will change default to logic 0 Ignore on read 1 = preamble may be suppressed 0 = preamble always required 1 = Auto-Negotiation complete 0 = Auto-Negotiation in progress When read as logic 1, indicates that the Auto-Negotiation process has been completed, and the contents of register 4, 5, 6 and 7 are valid. When read as logic 0, indicates that the Auto-Negotiation process has not been completed, and the contents of register 4, 5, 6 and 7 are meaningless. If Auto-Negotiation is disabled (bit 0.12 set to logic 0), then this bit will always read as logic 0. 0 1 1 1 1 1 0 32/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet The basic MII registers 1(continued) MII NAME R/W DESCRIPTION DEFAULT MII status register (address 01h) 1.4 Remote fault RO LH 1.3 Auto-Negotiation Ability RO 1.2 Link Status RO LL 1.1 Jabber Detect RO LH 1.0 Extended capability RO 1 = remote fault detected 0 = not remote fault detected When read as logic 1, indicates that IP113M LF has detected a remote fault condition. This bit is set until remote fault condition gone and before reading the contents of the register. This bit is cleared after IP113M LF reset. 1 = Auto-Negotiation capable 0 = not Auto-Negotiation capable When read as logic 1, indicates that IP113M LF has the ability to perform Auto-Negotiation. The value of this bit will depend on the external mode setting of IP113M LF operation mode. 1 = Link Pass 0 = Link Fail When read as logic 1, indicates that IP113M LF has determined a valid link has been established. When read as logic 0, indicates the link is not valid. This bit is cleared until a valid link has been established and before reading the contents of this registers. 1 = jabber condition detected 0 = no jabber condition detected When read as logic 1, indicates that IP113M LF has detected a jabber condition. This bit is always 0 for 100Mbps operation and is cleared after IP113M LF reset. This bit is set until jabber condition is cleared and reading the contents of the register. 1 = Extended register capabilities 0 = No extended register capabilities IP113M LF has extended register capabilities. 0 1 0 0 1 33/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet The basic MII registers 2 , 3 MII NAME R/W DESCRIPTION DEFAULT PHY Identifier (address 02h) 2[15:0] PHY identifier RO IP113M LF OUI (Organizationally Unique Identifier) ID, the msb is 3rd bit of IP113M LF OUI ID, and the lsb is 18th bit of IP113M LF OUI ID. IP113M LF OUI is 0090C3. 0243h MII NAME R/W DESCRIPTION DEFAULT PHY Identifier (address 03h) 3[15:10] PHY identifier RO RO RO 3[9:4] 3[3:0] Manufacture's Model Number Revision Number IP113M LF OUI ID, the msb is 19th bit of IP113M LF OUI ID, and lsb is 24th bit of IP113M LF OUI ID. TP110 model number IP113M LF revision number 3h 5h 0 34/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet The basic MII registers 4 MII NAME R/W DESCRIPTION DEFAULT Auto-Negotiation Advertisement register (address 04h) 4.15 Next Page RO 1 = Next Page ability is supported 0 = Next Page ability is not supported IP113M LF does not support next page, this bit is fixed to be 0. 0 4.14 4.13 Reserved Remote Fault RW R/W 4[12:11] Reserved Pause RO RW 4.10 4.9 4.8 4.7 4.6 4.5 4[4:0] 100BASE-T4 100BASE-TX full duplex 100BASE-TX 10BASE-T full duplex 10BASE-T Selector Field RW R/W R/W R/W R/W RO Reserved by IEEE, write as 0, ignore on read 1 = Advertises that this device has detected a remote fault 0 = No remote fault detected Reserved for future IEEE use, write as 0, ignore on read 1 = Advertises that this device has implemented pause function 0 = No pause function supported 1 = 100BASE-T4 is supported 0 = 100BASE-T4 is not supported 1 = 100BASE-TX full duplex is supported 0 = 100BASE-TX full duplex is not supported 1 = 100BASE-TX is supported 0 = 100BASE-TX is not supported 1 = 10BASE-T full duplex is supported 0 = 10BASE-T full duplex is not supported 1 = 10BASE-T is supported 0 = 10BASE-T is not supported Use to identify the type of message being sent by Auto-Negotiation. 0 0 0 Pin(1) 0 Pin(1) Pin(1) Pin(1) Pin(1) 00001 35/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet The basic MII registers 5 MII NAME R/W DESCRIPTION DEFAULT Link partner ability register (address 05h) Base Page 5.15 Next Page RO 1 = Next Page ability is supported by link partner 0 = Next Page ability is not supported by link partner 0 0 0 5.14 5.13 Acknowledge Remote Fault RO RO 5[12:10] Reserved 100BASE-T4 100BASE-TX full duplex 100BASE-TX 10BASE-T full duplex 10BASE-T Selector Field RO RO RO 5.9 5.8 5.7 5.6 5.5 5[4:0] RO RO RO RO 1 = Link partner has received the ability data word 0 = Not acknowledge 1 = Link partner indicates a remote fault 0 = No remote fault indicate by link partner If this bit is set to logic 1, then bit 1.4 (Remote fault) will set to logic 1. Reserved by IEEE for future use, write as 0, read as 0. 1 = Link partner support 100BASE-T4 0 = Link partner is not support 100BASE-T4 1 = Link partner support 100BASE-TX full duplex 0 = Link partner is not support 100BASE-TX full duplex 1 = Link partner support 100BASE-TX 0 = Link partner is not support 100BASE-TX 1 = Link partner support 10BASE-T full duplex 0 = Link partner is not support 10BASE-T full duplex 1 = Link partner support 10BASE-T 0 = Link partner is not support 10BASE-T Protocol selector of the link partner 0 0 0 0 0 0 00000 36/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet The basic MII registers 6 MII NAME R/W DESCRIPTION DEFAULT Auto-Negotiation Expansion register (address 06h) 6[15:5] Reserved RO Reserved by IEEE, writes as 0, ignore on read. 6.4 Parallel Detection Fault RO LH 6.3 6.2 6.1 6.0 Link Partner Next Page Able Next Page Able Page Received Link Partner Auto-Negotiation Able RO RO RO LH RO 1 = A fault has been detected via Parallel Detection function 0 = A fault has not detected via Parallel Detection function 1 = Link Partner is Next Page able 0 = Link Partner is not Next Page able 1 = Local Device is Next Page able 0 = Local Device is not Next Page able 1 = A New Page has been received 0 = A New Page has not been received 1 = Link Partner is Auto-Negotiation able 0 = Link Partner is not Auto-Negotiation able 0 0 0 1 0 0 37/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 3.2 MII Extended MII registers and EEPROM registers ROM NAME R/W DESCRIPTION DEFAULT EEPROM enable register 0 (EEPROM register 00D) -0[7:0] RO EEPROM enable register 0 This register should be filled with 55. IP113M LF will examine the specified pattern to confirm if there is a valid EEPROM. 55 MII ROM NAME R/W DESCRIPTION DEFAULT EEPROM enable register 1 (EEPROM register 01D) -1[7:0] RO EEPROM enable register 1 This register should be filled with AA. IP113M LF will examine the specified pattern to confirm if there is a valid EEPROM. The initial setting is updated with the content of EEPROM only if the specified pattern 55AA is found. AA 38/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 16 MII ROM NAME R/W DESCRIPTION DEFAULT Special control register (16D) 16.0 -- Reserved 16.1 16.2 16.3 ---- Reserved Reserved mr_bypass_scramble R/W 16.4 -- mr_bypass_100x _coder R/W 16.5 -- mr_bypass_dsp_rst R/W 16.6 -- mr_tx_nlp_disable R/W 16.7 -- mr_analog_pwsv _disable mr_fef_disable R/W 16.8 -- R/W 16.9 -- mr_jabber_enable R/W 16.10 -- mr_heart_beat _enable mr_auto_cross _disable R/W 16.11 -- R/W 16.12 16.13 16.14 16.15 ----- Reserved Reserved Reserved Reserved This bit should be "0" for normal operation. This bit should be "0" for normal operation. This bit should be "0" for normal operation. Bypass PCS scrambler (It is valid only if 16.15=1.) 1: bypass scrambler, 0: not bypass (default) This bit should be "0" for normal operation. Bypass PCS 4B/5B coder (It is valid only if 16.15=1.) 1: bypass 4B/5B, 0: not bypass (default) This bit should be "0" for normal operation. Bypass DSP re-start function in PCS 1: bypass DSP re-start, 0: not bypass (default) This bit should be "0" for normal operation. 10Mb transmit NLP enable 1: enable (default), 0:disable This bit should be "1" for normal operation. Analog power save mode disable 1: disable, 0: enable (default) The default value is recommended to adopt. Far-End-Fault function disable 1: disable, 0: enable (default) The default value is recommended to adopt. Jabber function enable 1: enable, 0:disable (default) The default value is recommended to adopt. Heart Beat function enable 1: enable, 0:disable (default) The default value is recommended to adopt. Auto Crossover function disable 1: disable, 0: enable (default) It should be disabled if MII register 0.12 auto-negotiation is disabled. This bit should be "0" for normal operation. This bit should be "0" for normal operation. This bit should be "0" for normal operation. 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 0 0 0 39/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 17 MII ROM NAME R/W DESCRIPTION DEFAULT Interrupt register (17D) 17.0 -intr_link RO RC 17.1 -- intr_duplex RO RC 17.2 -- intr_speed RO RC 17.3 -- intr_mf_rx_indicate RO RC 17.4 -- intr_cnt_overflow RO RC 17.5 -- intr_status RO RC RO RC 17.6 -- Intr_pwabn Link status change It is logic "1" when link status changes on TP port and it will active interrupt pin. It is self-clear after reading the register. 1: link status change Interrupt occur, 0: no interrupt Duplex mode change It is logic "1" when duplex status changes on TP port and it will active interrupt pin. It is self-clear after reading the register. 1: duplex status change Interrupt occur, 0: no interrupt Speed mode change It is logic "1" when speed changes on TP port and it will active interrupt pin. It is self-clear after reading the register. 1: speed change interrupt occur, 0: no interrupt Undefined maintenance frame receive indication It is logic "1" when an undefined maintenance frame is received and it will active interrupt pin. An undefined maintenance frame is a frame, which can't be recognized by IP113M LF. It is self-clear after reading the register. 1: Rx maintenance frame interrupt occur, 0: no interrupt Statistic counter overflow It is logic "1" when statistic counter is overflow and it will active interrupt pin. It is self-clear after reading the register. 1: counter overflow interrupt occur, 0: no interrupt Interrupt status It is logic "OR" of bit 17.0~17.4. 1: any interrupt occur, 0: no interrupt Power abnormal It is logic "1" when 113M receives a maintenance frame with link partner's power abnormal message and it will active interrupt pin. It is self-clear after reading the register. 1: remote link partner power abnormal 0: nothing happen 0 0 0 0 0 0 0 40/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 17(continued) MII ROM NAME R/W DESCRIPTION DEFAULT Interrupt register (17D) 17.7 -Intr_pwabn_en RW 17.8 -- intr_link_mask RW 17.9 -- intr_duplex_mask RW 17.10 -- intr_speed_mask RW 17.11 -- intr_mf_rx_indc _mask RW 17.12 -- intr_cnt_ov_mask RW 17.13 -- intr_all_mask RW Remote LP power abnormal interrupt enable A mask for bit 17.6. 1: not mask interrupt 0: mask interrupt Mask TP port link change Interrupt A mask for bit 17.0. 1: mask, 0: not mask (default) Mask TP port duplex mode change Interrupt A mask for bit 17.1. 1: mask interrupt (default), 0: not mask Mask TP port speed mode change Interrupt A mask for bit 17.2. 1: mask interrupt (default), 0: not mask Mask maintenance frame receive indication Interrupt A mask for bit 17.3. 1: mask interrupt (default), 0: not mask Mask Statistic counter overflow Interrupt A mask for bit 17.4. 1: mask interrupt (default), 0: not mask Mask all Interrupt It enables the all mask bits 17.7~17.12. 1: mask interrupt (default), 0: not mask 0 1 1 1 1 1 1 17[15:14] -- Reserved RW 0 41/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 18 MII ROM NAME R/W DESCRIPTION DEFAULT PHY extended status register (18D) 18[6:0] -Reserved[2:0] 18.7 -- jabber RO RO 18.8 -- polarity RO 18.9 -- mdix_en RO 18.10 -- link_real RO 18.11 -- resolved RO Jabber status 1: jabber is detected, 0: no jabber (default) It is a mirror bit of MII register 1 bit 1. Polarity status 1: polarity error, RXIP and RXIM are reversed, 0: polarity ok (default) MDI/MDIX status 0: MDI, TX and RX are normal on TP port. 1:MDIX, TX and RX are crossed over on TP port. TP port link Status 1: link ok, 0: link fail (default) It is a mirror bit of MII register 1 bit 2. Resolve complete 1: Auto-negotiation complete, 0: during Auto-negotiation (default) It is a mirror bit of MII register 1 bit 5. TP port duplex mode (It is valid only if 8.11=1.) 1: full duplex (default), 0: half duplex It is a mirror bit of MII register 0 bit 8. TP port speed mode (It is valid only if 18.11=1.) 1: 100M (default), 0: 10M It is a mirror bit of MII register 0 bit 13. 8d 0 0 0 0 0 18.12 18.13 --- Reserved mr_duplex_mode RO RO 0 0 18.14 -- mr_speed_selection RO 1 18.15 -- Reserved RO 0 42/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 19 MII ROM NAME R/W DESCRIPTION DEFAULT Statistic counter registers (MII register 19D) 19[11:0] -mg_statistic_cnt[11:0] RO Statistic Counter [11:0] The statistic counter maintains some kinds of statistic information. Before reading the statistic counter, user has to select one counter by writing MII register 19[14:12] cnt_index[2:0]. The relationship between cnt_index and its corresponding counter is shown in the following table. 0 Cnt_index Content of statistic counter[11:0] 3'b000 3'b001 3'b010 3'b011 3'b100 3'b101 3'b110 19[14:12] -cnt_index[2:0] RW Received packet count on TP port Received CRC error count on TP port Drop packet count on TP port Collision event count on TP port Received packet count on fiber port Received CRC error count on fiber port Drop packet count on fibe port 0 19.15 -- cnt_loop_en RW 3'b111 Collision event count on fiber port The current counter index A counter index to select one counter before reading MII register 19[11:0] The counter index loop enable 1: MII register 19[14:12] cnt_index[2:0] is increased by one automatically whenever the MII register 19 is read. Cnt_index[2:0] is turned arounf to "000" when it reaches to "111" and is read. 0: cnt_index[2:0] is not increased when MII register 19 is read. 1 43/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 20 MII ROM NAME R/W DESCRIPTION DEFAULT Switch configuration register 1 (MII register 20D, EEPROM register 02~03D) 20.0 2.0 Reserved 20.1 2.1 direct_wire R/W 20.2 2.2 fast_fwd R/W 20.3 2.3 mg_pass_fragment _en R/W 20.4 2.4 mg_col16_drop_en R/W 20.5 2.5 mg_col_backoff_en R/W 20.6 20.7 2.6 2.7 Reserved p01_mg_backpress _en R/W R/W 20.8 3.0 mg_rem_ctrl_en R/W 20.9 3.1 mg_auto_tx_mf_en R/W Please see pin description of DIRECT_WIRE for more detail information. This bit overwrites the setting on pin 22 DIRECT_WIRE. Please see pin description of FAST_FWD for more detail information. This bit overwrites the setting on pin 23 FAST_FWD. Pass fragment packet, which is longer than 7 bytes and shorter than 64bytes1: pass fragment 0: not pass fragment Collision 16 times drop enable A port drops a transmission packet if it experiences 16 consecutive collisions. 1: enable 0: disable Collision back-off enable 1: back off after collision 0: not back off after collision This bit should be "1" for normal operation. It must be 0. TP port backpressure enable Backpressure is flow control for half duplex operation 1: backpressure enable 0: backpressure disable Remote control enable 1: ability enable. IP113M LF is capable of transmission and receiving maintenance frame to perform remote control. 0: ability disable. IP113M LF is not capable of transmission and receiving maintenance frame to perform remote control. Auto send status frame to link partner through fiber port (AUTO_SEND) 1: auto send indication maintenance frame 0: disable auto send function This bit overwrites the setting on pin 25 AUTO_SEND. Please see pin description of AUTO_SEND for more detail information. 0 Pin (0) Pin (0) 0 0 1 0 1 1 Pin (0) 44/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 20(continued) MII ROM NAME R/W DESCRIPTION DEFAULT Switch configuration register 1 (MII register 20D, EEPROM register 02~03D) 20.10 3.2 mg_auto_tx_ttc R/W The format of auto send status frame _content 1: TTC (TS-1000) IP113M LF performs auto send functions with the frame format defined in TS-1000. 0: ICPLUS IP113M LF performs auto send functions with the ICPLUS proprietary frame format. The frame format is similar to the one defined in TS-1000 except the bit definition of S[15:0]. S[15:0] carries the content of MII register 22[15:0] local MC extended register. IP113M LF uses the frame to indicate its status to its link partner. The link partner, another IP113M LF, stores the information in the S[15:0] field of the frame to its MII register 23 after receiving the frame. 20.11 3.3 mg_sd_off_way R/W Informing way for optical receiving SD off 1: IP113M LF uses far end fault pattern to notify the link partner SD off information through fiber port. 0: IP113M LF uses maintenance frame to notify the link partner SD off information through fiber port. 1 1 20.12 20.13 3.4 3.5 Reserved tp_force R/W R/W 20.14 3.6 mg_receive_en R/W 20.15 3.7 p02_receive_on RO LL RC This bit should be "0" for normal operation. This pin overwrites the setting on pin 26 TP_FORCE. Please see pin description of TP_FORCE for more detail information. TP receive enable 1: TP port can receive packet 0: TP port drop all received packet This bit should be "1" for normal operation. Fiber port receive path ready 1: Fiber port receive path is ready (SD is on and normal IDLE pattern received) 0: Fiber port receive path is not ready 1 Pin (0) 1 0 45/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 21 MII ROM NAME R/W DESCRIPTION DEFAULT Switch configuration register 2 (MII register 21D, EEPROM register 04~05D) The register is for testing only. Access to this register may cause malfunction. 21[7:0] 4[7:0] Reserved R/W The default value must be adopted if uses use an EEPORM. 21[15:8] 5[7:0] 120d 120d Reserved R/W The default value must be adopted if uses use an EEPORM. 46/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 22 MII ROM NAME R/W DESCRIPTION DEFAULT Local MC extended register (MII register 22D, EEPROM register 06~07D) 22.0 6.0 mg_loopback_en R/W TP port loop-back test enable 1: loop back mode 0: normal mode It is a mirror bit of MII register 0 bit 14. 0 22.1 6.1 mg_status_rpt_en RO 22.2 6.2 p01_mg_auto_neg _en R/W 22.3 6.3 p01_mg_speed _mode p01_mg_duplex _mode R/W 22.4 6.4 R/W 22.5 6.5 p01_mg_flow_ctrl_ en R/W 22.6 22.7 6.6 6.7 p01_mg_link_status p02_mg_flow_ctrl_ en RO R/W 22.8 7.0 p02_mg_duplex _mode R/W 22.9 7.1 p02_mg_link_status RO LL RC RO LH RC 22.10 7.2 p02_mg_fef_detect TP port status (link, speed, duplex) available 1: TP status is valid 0: TP status is not ready TP port auto-negotiation enable 1: TP auto-negotiation enable 0: TP auto-negotiation disable It is a mirror bit of MII register 0 bit 12. TP port speed selection 1: 100M, 0:10M It is a mirror bit of MII register 0 bit 13. TP port duplex mode selection 1: full duplex, 0:half duplex It is a mirror bit of MII register 0 bit 8. This bit overwrites the setting on pin 30 DUPLEX_MODE. TP port flow control selection 1: on, 0:off It is a mirror bit of MII register 4 bit 10. This bit overwrites the setting on pin 29 X_EN for TP port. TP port link status off 1: link off, 0: link on Fiber port flow control/backpressure enable 1: enable, 0: disable This bit overwrites the setting on pin 29 X_EN for fiber port. Fiber port duplex mode 1: full duplex, 0:half duplex This bit overwrites the setting on pin 36 FX_FULL. Fiber port signal detect (power) 1: Fiber SD has been low since last read 0: Fiber SD is O.K. It is self-set after reading. Fiber port Far-End-Fault detect 1: FEF has been detected since last read 0: no FEF pattern detected It is self-clear after reading. 0 1 Pin (1) Pin (0) Pin (1) 1 Pin (1) Pin(1) 1 0 47/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 22(continued) MII ROM NAME R/W DESCRIPTION DEFAULT Local MC extended register (MII register 22D, EEPROM register 06~07D) 22[12:11] 7[4:3] p01_mg_throttle R/W TP port input Rate Control _confg IP113M LF limits the input traffic of TP port. 00 22[14:13] 7[6:5] p01_mg_throttle _confg R/W 22.15 7.7 mg_link_pass_en R/W Traffic 10M mode 100M mode 00 10Mbps 100Mbps 01 2.5Mbps 25Mbps 10 5Mbps 50Mbps 11 7.5Mbps 75Mbps TP port output Rate Control IP113M LF limits the output traffic of TP port. Traffic 10M mode 100M mode 00 10Mbps 100Mbps 01 2.5Mbps 25Mbps 10 5Mbps 50Mbps 11 7.5Mbps 75Mbps Link Fault Pass through enable (LFP) 1: enable, 0: disable This bit overwrites the setting on pin 21 LFP. 00 Pin (0) 48/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 23 MII ROM NAME R/W DESCRIPTION DEFAULT Link partner MC extended status register (MII register 23D) 23.0 -lp_loopback_en RO Loop-back enable of remote LP 1: Link partner's fiber port is in loop back mode. Its fiber port will forward all receiving frames from FXRDP/M to FXTDP/M.. 0: Link partner's fiber port is in normal mode 0 23.1 -- lp_status_rpt_en RO 23.2 -- lp_tp_autoneg_en RO 23.3 -- lp_tp_speed_mode RO 23.4 -- lp_tp_duplex_mode RO 23.5 -- lp_tp_flow_ctrl_en RO 23.6 -- lp_tp_link_off RO 23.7 -- lp_fb_flow_ctrl_en RO 23.8 -- lp_fb_duplex_mode RO Option B support 1: Link partner supports TS-1000 option B 0: not support TP port auto-negotiation enable 1: Link supports aut0-negotuation, 0: Link partner doesn't support auto-negotiation. TP port speed of link partner 1: 100M, 0:10M TP port duplex mode of link partner 1: full duplex, 0: half duplex TP port flow control of link partner. 1: flow control enable 0: flow control disable This bit is valid only if MII register 20 bit10 is set to be 0. TP port link status of link partner 1: link off, 0:link on Fiber port flow control/backpressure of link partner This bit is valid only if MII register 20 bit10 is set to be 0. 1: flow control enable 0: flow control disable Fiber port duplex mode of link partner 1: full duplex, 0: half duplex This bit is valid only if MII register 20 bit10 is set to be 0. Fiber port signal detect status of link partner 1: off, 0: on This bit is valid only if MII register 20 bit10 is set to be 0. 0 0 0 0 0 1 0 0 23.9 -- lp_fb_link_status RO 0 49/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 23(continued) MII ROM NAME R/W DESCRIPTION DEFAULT Link partner MC extended status register (MII register 23D) 23.10 -- reserved RO 23.11 -- lp_power_abnormal RO 23.12 -- lp_mc_failed RO 23.13 -- lp_sd_off_way RO 23.14 -- lp_multi_tp_port RO 23.15 -- mg_link_pass_en RO Power status of link partner 1: power abnormal 0: power O.K. MC failed 1: link partner malfunctions 0: link partner is normal Link Partner informing way of SD off 1: Link partner sends far end fault pattern when its SD is off. 0: Link partner sends maintenance frame when its SD is off. MC support multi-port UTP 1: Link partner supports more than one TP port 0: Link partner supports one TP port Link Fault Pass through enable 1: Link partner supports Link Fault Pass Through function 0: Link partner doesn't support Link Fault Pass Through function This bit is valid only if MII register 20 bit10 is set to be 0. 0 0 0 1 0 0 50/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 24 MII ROM NAME R/W DESCRIPTION DEFAULT Remote control Transmit register 1 (MII register 24D) 24.0 -mg_rem_tx_code R/W Remote control frame send trigger 1: command IP113M LF to send a maintenance frame 0: does not command IP113M LF to send a maintenance frame If user wants to send another maintenance frame, he has to write "1" to this bit again. 0 24.1 -- mg_rem_tx_code R/W Transmitted maintenance direction discriminator C1 It is C1 field of a maintenance frame. 0: upstream 1: downstream Transmitted maintenance frame command discriminator C3~C2 It is C[3:2] field of a maintenance frame. 01: request 11: acknowledge 10: Indication 00: reserved Transmitted maintenance frame control signals C15~C8 It is C[15:8] field of a maintenance frame. Bit11(C15) ........bit4(C8) 00000 00000 00000 Address [4:0] 0 0 0 01 00 10 Function Loop test start Loop test finished Status indication R/W link partner's registers 0 24[3:2] -- mg_rem_tx_code R/W 00 24[11:4] -- mg_rem_tx_code R/W 8'b0 R/W 11 Note: R/W: 0: read, 1: write A[4:0]: register address 24[15:12] -Reserved 51/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 25 MII ROM NAME R/W DESCRIPTION DEFAULT Remote control Transmit register 2 (MII register 25D) 25[15:0] -mg_rem_wt_data R/W Remote control write data If a remote write command is issued, that is, MII register 24[6:4] is programmed as 111. The content in this register will be embedded into S[15:0] of a maintenance and is sent to the link partner. The link partner, an IP113M LF, will update the addressed MII register with the value defined in this register after receiving the remote write command. 16'b0 52/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 26 MII ROM NAME R/W DESCRIPTION DEFAULT Remote control Receive register 1 (MII register 26D) 26.0 -mg_rem_rx_code RO Receive an acknowledge maintenance, that RC is field C[2:3]=11, or undefined maintenance frame. 1: IP113M LF receives a response (acknowledge) maintenance frame or undefined maintenance frame. 0: no response (acknowledge) maintenance frame or undefined maintenance frame received. User can poll this bit to make sure if there is an acknowledge maintenance frame or an undefined maintenance frame is received. It is a read and auto-clear bit. Note: register 26~30 will be updated only when this bit is 1. 26.1 -mg_rem_rx_code RO Direction discriminator C1 of a received maintenance frame. 0 0 00 8'b0 26[3:2] 26[11:4] 26[12] ---- mg_rem_rx_code mg_rem_rx_code mg_rem_rx_code RO RO RO RC Command discriminator C3~C2 of a received maintenance frame. control signals C15~C8 of a received maintenance frame. Received maintenance frame CRC error 1: received a maintenance frame with CRC error. 0: received a maintenance frame with correct CRC . It is a read and auto-clear bit. 26[15:13] -- Reserved 53/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 27,28,29,30 MII ROM NAME R/W DESCRIPTION DEFAULT Remote control Receive register 2 (MII register 27D) 27[15:0] -mg_rem_rd_data RO Remote read data The link partner will send out a maintenance frame carrying remote-read data if IP113M LF issues a remote-read command by sending a maintenance frame. It is derived from the S[15:0] field of a received maintenance frame sent by the link partner. 16'b0 MII ROM NAME R/W DESCRIPTION DEFAULT Remote control Receive register 3 (MII register 28D) 28[15:0] -mg_rem_rd_data RO Vender message M0~M15 The M[15:0] field of a received maintenance frame sent by the link partner. 16'b0 MII ROM NAME R/W DESCRIPTION DEFAULT Remote control Receive register 4 (MII register 29D) 29[15:0] -mg_rem_rd_data RO Vender message M16~M31 The M[31:16] field of a received maintenance frame sent by the link partner. 16'b0 MII ROM NAME R/W DESCRIPTION DEFAULT Remote control Receive register 5 (MII register 30D) 30[15:0] -mg_rem_rd_data RO Vender message M32~M47 The M[47:32] field of a received maintenance frame sent by the link partner. 16'b0 54/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet Extended MII registers and EEPROM registers 31 MII ROM NAME R/W DESCRIPTION DEFAULT Switch configuration register 3 (MII register 31D) 31.0 -- software_reset R/W Chip software reset SC Reset IP113M LF without updating the content of registers. It is a self-clear bit. 1: reset, 0: not reset 0 31.1 -- mg_power_indicate _disable R/W 31.2 -- TP_link_list_fail RO IP113M LF power abnormal indication disable 1: IP113M LF does not send out maintenance frame with power abnormal message when its power is abnormal 0: IP113M LF sends out maintenance frame with power abnormal message when its power is abnormal TP port link list failure indication 1: TP port memory link list fails 0: TP port memory link list is ok This bit is always 0, if IP113M LF is in normal operation. Fiber port link list failure indication 1: Fiber port memory link list fails 0: Fiber port memory link list is ok This bit is always 0, if IP113M LF is in normal operation. BIST Status of embedded SSRAM bit[4] : memory is under testing 1: under testing, 0: testing over bit[5] : memory test result is good when testing over 1: good, 0: fail Bit[5:4] is "01" at the end of reset. After BIST, If the test result is ok, it becomes "10", otherwise it shows "00". Auto loopback test enable 1: start an auto loopback test procedure, 0:does not perform auto loop back test Loopback test T2 timer disabled Disable the function of T2 timer defined in TS-1000. 1: IP113M LF does not send loopback end indication maintenance frame when T2 timer expires 0: IP113M LF sends loopback end maintenance frame when T2 timer expires Auto loopback test complete 1: loopback test is completed, 0: under testing 55/58 0 0 31.3 -- Fiber_link_list_fail RO 0 31[5:4] -- BIST_status RO 01 31.6 -- mg_auto_loopback _test mg_t2_timer_disable R/W 0 31.7 -- R/W 0 31.8 -- mg_auto_loopback _complete RO 0 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 31.9 -mg_auto_loopback _ok Reserved RO Auto loopback test OK 1: loopback test result is ok 0: loopback test result fails 0 31[15:10] -- 56/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 4. Electrical Characteristics 4.1 Absolute Maximum Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional performance and device reliability are not guaranteed under these conditions. All voltages are specified with respect to GND. Supply Voltage -0.3V to Vcc+0.3V Input Voltage -0.3V to Vcc+0.3V Output Voltage -0.3V to Vcc+0.3V Storage Temperature -55C to 125C Ambient Operating Temperature (Ta) 0C to 70C 4.2. DC Characteristic Sym. VCC Min. 2.375 Typ. 2.5 0.475 Max. 2.645 Unit V W Conditions Operating Conditions Parameter Supply Voltage Power Consumption Input Clock Parameter Frequency Frequency Tolerance I/O Electrical Characteristics Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Sym. VIL Min. Typ. Max. 0.8 Unit V Conditions Sym. Min. Typ. Max. Unit MHz PPM Conditions VCC=2.5v 25 -100 +100 VIH VOL VOH 2.0 0.4 VCC_I O-0.4 V V V IOH=4mA IOL=4mA 5. Order Information Part No. IP113M Package 48-PIN LQFP Notice - IP113M LF 48-PIN LQFP Lead free 57/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 IP113M LF Preliminary Data Sheet 6. Package Detail 48 37 1 36 PH 12 25 13 HE 24 12" "E" D A2 GAUGE PLANE L L1 DETAIL "E" Symbol A unit A1 A2 b c D E mm 1.600MAX. 0.050~0.150 1.400 + 0.05 0.200TYP 0.127TYP 7.000 + 0.100 7.000 + 0.100 0.500TYP 9.000 + 0.250 9.000 + 0.250 0.600 + 0.150 1.000REF 0.100MAX. 0"~7" A1 F SEATING PLANE Fy 0.254 e E b 12" D 13 24 c inch 0.0630M AX. 0.0020~0.0059 0.0551 + 0.0020 0.0078TYP 0.0050TYP 0.2756 + 0.0039 0.2756 + 0.0039 0.0196TYP 0.3543 + 0.0098 0.3543 + 0.0098 0.0236 + 0.006 0.0393REF 0.0039M AX. 0"~7" 12 2 25 - - 2 e 36 Hd He L L1 - - 1 - - 48 37 y Notes: 1. DIMENSION D & E DO NOT INCLUDE MOLD FLASH OR PRO TRUSION. 2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION / INTRUSION. 3. M AX. END FLASH IS 0.15MM . 4. M AX. DAMBAR PROTRUSION IS 0.13M M . GENERAL APPEARANCE SPEC SHO ULD BE BASED ON FINAL VISUAL INSPECTION SPEC. IC Plus Corp. Headquarters 10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2, Hsin-Chu City, Taiwan 300, R.O.C. TEL : 886-3-575-0275 FAX : 886-3-575-0475 Website : www.icplus.com.tw Sales Office 4F, No. 106, Hsin-Tai-Wu Road, Sec.1, Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C. TEL : 886-2-2696-1669 FAX : 886-2-2696-2220 58/58 Copyright (c) 2004, IC Plus Corp. April 9, 2007 IP113M LF-DS-R11 A |
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